1. Field of the Invention
The present invention relates to a data transfer apparatus for inter-circuit serial transfer of data inside a system LSI.
2. Description of the Related Art
In recent years, a system LSI has been increasing in size with more functions incorporated therein, along with which circuits and wirings used for inter-circuit data transfer inside the system LSI have also been increasing. The wirings, in particular, which actually serve to connect the internal components in the system LSI, take up a large percentage of a wiring resource in the system LSI, directly lead to the increase of the system LSI in size, that is, the increase of costs.
To deal with the situation, a method for serially connecting the circuits in the system LSI has been proposed. FIG. 17A shows a conventional data transfer apparatus according to the method, which comprises a transmission data bus 90, flip-flops 91a–91e, selectors 92a–92d, a buffer 93, a multiplier (PLL) 94 and the like, and operates as shown in FIG. 17B.
More specifically, a system clock CLK is multiplied by means of the multiplier 94 so that a high-speed transmission enable signal Ssen is generated and applied to clock inputs of the flip-flops 91a–91d. 
When a data set signal DS is in an asserted state at a “L” level, the selectors 92a–92d select an “L” level input and outputs respective bits A3–A0 on the transmission data bus 90, whereas the buffer 93 outputs a consecutive signal at the “L” level because the flip-flop 91e in the final stage as a transfer gate is closed.
In response to the shift of the data set signal DS to an “H” level, the data transfer apparatus goes to a serial transfer mode. The flip-flops 91a–91d and the selectors 92a–92d are thereby serially connected. Further, a transfer clock Str with respect to the transfer gate 91e is raised from the “L” level to the “H” level. Thereby, whenever the transmission enable signal Ssen from the multiplier 94 rises, respective bit values are serially outputted from the transfer gate 91e and the buffer 93.
The serial transfer according to the conventional technology is realized by means of a clock signal. Therefore, the clock higher than a clock essentially required for the system is indispensable for the realization of a high-speed transfer. That is the reason why the multiplier 94 generating such a clock is necessarily provided.